Dimensioning and Modulation Index Selection for the Hybrid Modular Multilevel Converter

The Hybrid MMC, comprising a mixture of fullbridge and half-bridge sub-modules, provides tolerance to DC faults without compromising the efficiency of the converter to a large extent. The inclusion of full-bridges creates a new freedom over the choice of ratio of AC to DC voltage at which the converter is operated, with resulting impact on the converter’s internal voltage, current and energy deviation waveforms, all of which impact the design of the converter. A design method accounting for this, and allowing the required level of derating of nominal sub-module voltage and up-rating of stack voltage capability to ensure correct operation at the extremes of the operating envelope is presented. A mechanism is identified for balancing the peak voltage that the full-bridge and halfbridge sub-modules experience over a cycle. Comparisons are made between converters designed to block DC side faults and converters that also add STATCOM capability. Results indicate that operating at a modulation index of 1.2 gives a good compromise between reduced power losses and additional required sub-modules and semiconductor devices in the converter. The design method is verified against simulation results and the operation of the converter at the proposed modulation index is demonstrated at laboratory-scale

Power-System Level Classification of Voltage-Source HVDC Converter Stations Based Upon DC Fault Handling Capabilities

status: publishe

The Extended Overlap Alternate Arm Converter:A Voltage Source Converter with DC Fault Ride-Through Capability and a Compact Design

The Alternate Arm Converter (AAC) was one of the first modular converter topologies to feature DC-side fault ride-through capability with only a small penalty in power efficiency. However, the simple alternation of its arm conduction periods (with an additional short overlap period) resulted in (i) substantial 6-pulse ripples in the DC current waveform, (ii) large DC-side filter requirements, and (iii) limited operating area close to an energy sweet-spot. This paper presents a new mode of operation called Extended Overlap (EO) based on the extension of the overlap period to 60 ◦ which facilitates a fundamental redefinition of the working principles of the AAC. The EO-AAC has its DC current path decoupled from the AC current paths, a fact allowing (i) smooth DC current waveforms, (ii) elimination of DC filters, and (iii) restriction lifting on the feasible operating point. Analysis of this new mode and EO- AAC design criteria are presented and subsequently verified with tests on an experimental prototype. Finally, a comparison with other modular converters demonstrates that the EO-AAC is at least as power efficient as a hybrid MMC (i.e. a DC fault ride-through capable MMC) while offering a smaller converter footprint because of a reduced requirement for energy storage in the submodules and a reduced inductor volume

Cascaded- and Modular-Multilevel Converter Laboratory Test System Options: A Review

The increasing importance of cascaded multilevel converters (CMCs), and the sub-category of modular multilevel converters (MMCs), is illustrated by their wide use in high voltage DC connections and in static compensators. Research is being undertaken into the use of these complex pieces of hardware and software for a variety of grid support services, on top of fundamental frequency power injection, requiring improved control for non-traditional duties. To validate these results, small-scale laboratory hardware prototypes are often required. Such systems have been built by many research teams around the globe and are also increasingly commercially available. Few publications go into detail on the construction options for prototype CMCs, and there is a lack of information on both design considerations and lessons learned from the build process, which will hinder research and the best application of these important units. This paper reviews options, gives key examples from leading research teams, and summarizes knowledge gained in the development of test rigs to clarify design considerations when constructing laboratory-scale CMCs.This work was supported in part by The University of Manchester supported by the National Innovation Allowance project ``VSC-HVDC Model Validation and Improvement'' and Dr. Heath's iCASE Ph.D. studentship supported through Engineering and Physical Sciences Research Council (EPSRC) and National Grid, in part by the Imperial College London supported by EPSRC through the HubNet Extension under Grant EP/N030028/1, in part by an iCASE Ph.D. Studentship supported by EPSRC and EDF Energy and the CDT in Future Power Networks under Grant EP/L015471/1, in part by University of New South Wales (UNSW) supported by the Solar Flagships Program through the Education Infrastructure Fund (EIF), in part by the Australian Research Council through the Discovery Early Career Research Award under Grant DECRA_DE170100370, in part by the Basque Government through the project HVDC-LINK3 under Grant ELKARTEK KK-2017/00083, in part by the L2EP research group at the University of Lille supported by the French TSO (RTE), and in part by the Hauts-de-France region of France with the European Regional Development Fund under Grant FEDER 17007725

The impact of fault blocking converters on HVDC protection

Multiterminal High Voltage Direct Current (HVDC) systems are anticipated to enable flexible transmission of renewable energy across continents, however protection strategies for such systems are in their infancy. Fast circuit breakers have been proposed, however their implementation on a network is undecided. The protection requirements are likely to depend on both the AC/DC converter and network topologies. This thesis examines several aspects of the protection of HVDC systems, considering factors influencing circuit breaker ratings, and examining primary and backup protection philosophies. A comparison is made throughout between fault feeding and fault blocking converters, aiming to investigate the impact of fault blocking converters on HVDC protection. The ratings of HVDC circuit breakers on meshed networks are evaluated, considering factors such as the current breaking magnitude, operation time, additional inductance and energy dissipation requirements for various network and converter topologies. It is shown that the circuit breaker requirements in network areas with fault blocking converters are reduced compared to when a fault feeding converter is implemented. HVDC protection is investigated, considering primary and backup methods for several protection philosophies. The influence of the converter, network and circuit breaker topologies are examined, and the impact of the HVDC protection strategy on the connected AC systems is evaluated. It is shown that slower protection strategies using fault blocking converters might be technically feasible from both the HVDC and AC system perspectives, which could result in an effective protection strategy with a reduced requirement for circuit breakers.Open Acces

Testing procedures for HVDC grid protection IED

Presentation in panel session on the use of Real-time simulations at IEEE PowerTech 2019status: publishe

Small Scale HVDC Circuit Breaker

ISSN:2156-3950ISSN:2156-398

Testing of an HVDC IED Prototype Using Field Recordings

Testing of protection intelligent electronic devices (IEDs) for high-voltage direct-current (HVDC) systems is usually constrained to simulated HVDC faults because systematic testing with faults on full-scale HVDC systems is not feasible. However, all simulations are subject to inaccuracies. In this paper, an HVDC IED prototype is tested with real fault recordings from an operational point-to-point HVDC link. Firstly, the successful response of the prototype HVDC IED to fault recordings from a real system is presented. Secondly, the behaviour of different protection algorithms and filters is analysed, leading to conclusions about the applicability in a real system. The results are useful because the gained knowledge is based on both a real prototype HVDC IED and a real fault recording, and not a simulation.QC 20220603Part of proceedings: ISBN 978-907581537-5</p

HVDC Grid Protection Algorithm Performance Assessment

status: publishe